1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a capacitor.
2. Description of the Background Art
In a semiconductor device having a capacitor, such as DRAM (dynamic random access memory), since the capacitor capacitance does not response to the scaling law of high integration only by improving the capacitor structure, it is now considered to use materials of high dielectric constant, such as Ta2O5, (Ba, Sr)TiO3, Pb(Zr, Ti)O3, Pb(La, Ti) O3 and SBT (SrBi2Ta2O9) as a dielectric to form a capacitor insulating film.
Further, as to a nonvolatile memory, ferroelectric memory utilizing polarization reversal of ferroelectrics is being developed.
In a case where a capacitor insulating film is formed of a material of high dielectric constant such as above, a capacitor electrode is generally formed mainly of a platinum-group element or an oxide of a platinum-group element.
Since the platinum-group element generally has a characteristic of low vapor pressure in a compound, an etching with ions of high energy, i.e., sputter etching is used in electrode formation. This method is a physical etching, and has problems that the selection ratio of mask material and workpiece is small, that the etching section has a tapered shape and microfabrication is difficult.
Then, a technique such as reactive ion etching using chemical etching method as well as physical etching with the wafer temperature kept high and the vapor pressure of reactive compound raised higher has been considered. This method uses a heat-resistant material such as a silicon oxide film, a silicon nitride film and a titanium nitride film, i.e., a hardmask as a mask material for electrode formation.
Hereafter, a background-art manufacturing method using reactive ion etching will be discussed, referring to cross sections of FIGS. 15 to 21 showing the manufacturing process step by step.
First, in the step of FIG. 15, a silicon substrate 1 is prepared and an isolation insulating film 3 which electrically isolates elements and defines an active region which is to become an element formation region is formed. On the active region defined by the isolation insulating film 3, a gate insulating film 4 and a gate electrode 5 of a MOS transistor are selectively formed. Then, an impurity diffusion layer 2 which is to become a source/drain layer is selectively formed in a main surface of the silicon substrate 1 with the gate electrode 5 used as a mask.
After that, an interlayer insulating film 6 is so formed on the silicon substrate 1 as to completely cover the MOS transistor. At this time, a contact plug 7 (bit line contact) connected to a predetermined impurity diffusion layer 2 and a bit line 8 electrically connected to the predetermined impurity diffusion layer 2 through the contact plug 7 are formed in the interlayer insulating film 6.
After forming a silicon nitride film 11 on the interlayer insulating film 6 as an etching stopper, a plurality of contact plugs 10 (storage node contacts) penetrating the interlayer insulating film 6 and the silicon nitride film 11 to be connected to the predetermined impurity diffusion layer 2 are formed. Further, the contact plugs 7 and 10 are each formed of a conductor such as polysilicon.
Next, in the step of FIG. 16, a platinum film 12 and a silicon oxide film 13 are formed in this order on the silicon nitride film 11. After that, a resist mask RM1 which is so patterned as to correspond to a pattern of a capacitor lower electrode (storage node) is formed on the silicon oxide film 13.
Next, in the step of FIG. 17, the silicon oxide film 13 is patterned with the resist mask RM1 used as an etching mask. This serves as a hardmask.
Next, in the step of FIG. 18, the platinum film 12 is patterned with this hardmask used as an etching mask, to form the capacitor lower electrode. After that, the silicon oxide film 13 serving as the hardmask is removed with the silicon nitride film 11 in an underlying layer located below the capacitor used as an etching stopper.
Next, in the step of FIG. 19, a capacitor dielectric film 14 is so formed as to cover the platinum film 12 serving as the capacitor lower electrode and on the capacitor dielectric film 14, a conductive film is formed as a capacitor upper electrode 15. The capacitor lower electrode 12, the capacitor dielectric film 14 and the capacitor upper electrode 15 constitute a capacitor CP.
Further, besides the above-discussed background-art method, Japanese Patent Application Laid Open Gazette No. 9-266200 discloses a manufacturing technique as below, which is intended to achieve an easy microfabrication of ferroelectrics or platinum electrode.
Specifically, on a device insulating film formed on a semiconductor substrate, a multilayer film consisting of a lower platinum film, a ferroelectric film and an upper platinum film is formed and on the multilayer film, a titanium film whose thickness is a tenth or less of that of the multilayer film is formed. After patterning the titanium film with a photoresist film, the multilayer film is etched with a mixed gas of oxygen and chlorine, whose oxygen concentration is 40%, with the patterned titanium film used as an etching mask. After that, the titanium film is removed by etching with a chlorine gas.
Furthermore, Japanese Patent Application Laid Open Gazette No. 2000-183303 discloses a manufacturing technique as below, which is intended to achieve a microfabrication of ruthenium electrode with excellent anisotropy.
Specifically, on a silicon oxide film, a multilayer film consisting of a silicon nitride film, a ruthenium film and a platinum film is formed and on the multilayer film, another silicon oxide film is formed. After patterning the higher silicon oxide film with a photoresist film, the platinum film and the ruthenium film are etched with the patterned silicon oxide film used as an etching mask. Finally, the silicon oxide film used as the etching mask is removed with the silicon nitride film formed below the ruthenium film as an etching stopper.
In these cases, there is a problem in the step of patterning the capacitor lower electrode formed of a platinum-group element. Though the chemical etching contributes to the etching of the platinum-group element as discussed earlier, the platinum-group element has an etching characteristic of large temperature dependency and due to the temperature distribution on a wafer or among a plurality of wafers processed simultaneously, an etching speed (etching rate) disadvantageously becomes nonuniform on the wafer surface or among the simultaneously-processed wafers.
FIG. 20 shows the temperature dependencies in etching rates of platinum (Pt), silicon nitride film (SiN) and silicon oxide film (SiO2) in patterning the capacitor lower electrode, for example, under the etching condition that a chlorine gas and an argon gas are used as etching gas with respective flows of 120 sccm and 30 sccm and the pressure in a reaction chamber is 20xc3x970.1333 Pa (20 mTorr).
In FIG. 20, the horizontal axis indicates wafer temperature (xc2x0C) and the vertical axis indicates etching rate (nm/min). As is clear from this graph, the temperature dependency of platinum (Pt) is considerably large.
This means that the etching rate of a platinum film is greatly affected by the temperature distribution on a wafer or among a plurality of wafers.
It is assumed now that the preset temperature of the wafer is 370xc2x0 C. and the platinum film 12 having a thickness of 20 nm formed on the silicon nitride film 11 is patterned in the above-discussed manufacturing process. There arises a temperature distribution where the lowest temperature region has a temperature of 360xc2x0 C. and the highest temperature region has a temperature of 380xc2x0 C. on the main surface of the silicon substrate 1, and there is a temperature difference of 20xc2x0 C. on the main surface of the silicon substrate 1.
If the amount of overetching in the lowest temperature region (360xc2x0 C.) is 10%, the etching time for the platinum film 12 is three minutes and forty seconds which is obtained from the characteristics shown in FIG. 20. In this case, the amount of etching of the silicon nitride film 11 in the underlying layer is 37 nm.
On the other hand, the etching time for the platinum film 12 in the highest temperature region (380xc2x0 C.) is about two minutes and twenty seconds which is obtained from the characteristics shown in FIG. 20, and therefore the silicon nitride film 11 in the underlying layer is etched for remaining one minute and twenty seconds and the amount of etching thereof is as much as 142 nm.
Herein, the etching state of the platinum film 12 in the case where the above temperature distribution is present is schematically shown in FIG. 21. Further, FIG. 21 shows a process step of FIG. 18 but the structure of the MOS transistor and the like are omitted for simplification.
As shown in FIG. 21, since the height of the platinum film 12 including a protrusion of the silicon nitride film 11 varies from 237 nm to 342 nm on a substrate, the aspect ratio varies depending on portions and it therefore becomes difficult to cover the film with the later-formed capacitor dielectric film at a uniform thickness.
FIG. 22 shows a state where the capacitor dielectric film 14 and the capacitor upper electrode 15 are formed.
As shown in FIG. 22, due to the variation in the amount of etching of the silicon nitride film 11, there arises a distribution of thickness of the silicon nitride film 11 on a substrate. This causes a variation in parasitic capacitance PC between the capacitor upper electrode 15 and an interconnection layer provided in the interlayer insulating film 6, such as the bit line 8, making a capacitance design difficult.
It is an object of the present invention is to solve the problem of nonuniform etching which is caused by the temperature distribution on a substrate or among a plurality of substrates when a capacitor lower electrode is patterned by chemical etching.
According to a first aspect of the present invention, the method of manufacturing a semiconductor device which includes a capacitor having a lower electrode selectively formed on an underlying layer, a dielectric film covering the lower electrode and an upper electrode opposed to the lower electrode with the dielectric film interposed therebetween includes the following steps (a) to (f).
The step (a) is to form first and second etching stopper films whose materials are different from each other in this order as the underlying layer on an interlayer insulating film. The step (b) is to form a conductive film which is to become the lower electrode on the second etching stopper film. The step (c) is to form a hardmask having a pattern corresponding to a plane pattern of the lower electrode on the conductive film. The step (d) is to from the lower electrode patterning at least the conductive film with the hardmask used as an etching mask and the second etching stopper film as an etching stopper. The step (e) is to completely remove at least the second etching stopper film other than a portion below the lower electrode with the first etching stopper film used as an etching stopper. The step (f) is to form the dielectric film and the upper electrode as to cover the lower electrode and the second etching stopper film remaining below the lower electrode.
Since the lower electrode is formed by patterning at least the conductive film with the second etching stopper film as an etching stopper and at least the second etching stopper film other than a portion below the lower electrode is completely removed with the first etching stopper film used as an etching stopper, when the conductive film is patterned by chemical etching, the etching thickness of the second etching stopper film located below the lower electrode is defined uniformly with the thickness of the second etching stopper film even if there is a temperature distribution on a substrate or among a plurality of substrates. Therefore, it is possible to solve the problem of nonuniform etching of the underlying layer caused by the temperature distribution and provide the dielectric film of uniform thickness which covers the lower electrode. Further, when an interconnection layer is formed in the interlayer insulating film, the parasitic capacitance between the interconnection layer and the upper electrode also becomes uniform and this allows an easy capacitance design.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.